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System Memory Controller (SMC)
3
❏ Error Notification for SDRAM
– Software programmable Interrupt on Single/Double-Bit Error.
– Error address and Syndrome Log Registers for Error Logging.
– Does not provide TEA_ on Double-Bit Error. (Chip has no
TEA_ pin.)
❏ ROM/Flash Interface
– Two blocks with each block being 16 or 64 bits wide.
– Programmable access time on a per-block basis.
❏ I2C master interface.
❏ External status/control register support
Block Diagrams
Figure 3-1 depicts a Hawk as it would be connected with SDRAMs in a
system. Figure 3-2 shows the SMC’s internal data paths. Figure 3-3 shows
the overall SDRAM connections. Figure 3-4 shows a block diagram of the
SMC portion of the Hawk ASIC.
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