Motorola MVME2400 Series Manuel de service Page 262

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3-76 Computer Group Literature Center Web Site
System Memory Controller (SMC)
3
Software Considerations
This section contains information that will be useful in programming a
system that uses the Hawk.
Programming ROM/Flash Devices
Those who program devices to be controlled by the Hawk should make
note of the address mapping that is shown in Table 3-7 and in Table 3-8.
For example, when using 8-bit devices, the code will be split so that every
other 4-byte segment goes in each device.
Writing to the Control Registers
Software should not change control register bits that affect SDRAM
operation while SDRAM is being accessed. Because of pipelining,
software should always make sure that the two accesses before and after
the updating of critical bits are not SDRAM accesses. A possible scenario
for trouble would be to execute code out of SDRAM while updating the
critical SDRAM control register bits. The preferred method is to be
executing code out of ROM/Flash and avoiding SDRAM accesses while
updating these bits.
Some registers have additional requirements for writing. For more
information refer to the register sections in this chapter titled “SDRAM
Enable and Size Register (Blocks A,B,C,D)”, “SDRAM Base Address
Register (Blocks A/B/C/D)”, “SDRAM Enable and Size Register (Blocks
E,F,G,H)”, “SDRAM Base Address Register (Blocks E/F/G/H)”, and
“SDRAM Speed Attributes Register.”
Since software has no way of controlling refresh/scrub accesses to
SDRAM, the hardware is designed so that updating control bits
coincidentally with refreshes is not a problem.
As with SDRAM control bits, software should not change control bits that
affect ROM/Flash while the affected Block is being accessed. This
generally means that the ROM/Flash size, base address, enable, write
enable, etc. are changed only while executing initially in the reset vector
area ($FFF00000 - $FFFFFFFF).
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