Motorola MVME2400 Series Manuel de service Page 15

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xv
List of Figures
Figure 1-1. MVME2400 Series System Block Diagram ...........................................1-6
Figure 1-2. VMEbus Master Mapping.....................................................................1-22
Figure 1-3. VMEbus Slave Mapping.......................................................................1-24
Figure 1-4. General-Purpose Software-Readable Header........................................1-30
Figure 2-1. Hawk’s PCI Host Bridge Block Diagram ...............................................2-3
Figure 2-2. PPC to PCI Address Decoding................................................................2-6
Figure 2-3. PPC to PCI Address Translation .............................................................2-7
Figure 2-4. PCI to PPC Address Decoding..............................................................2-19
Figure 2-5. PCI to PPC Address Translation ...........................................................2-20
Figure 2-6. PCI Spread I/O Address Translation.....................................................2-30
Figure 2-7. Big to Little Endian Data Swap ............................................................2-38
Figure 2-8. Serial Mode Interrupt Scan ...................................................................2-51
Figure 2-9. MPIC Block Diagram ...........................................................................2-56
Figure 3-1. Hawk Used with Synchronous DRAM in a System ..............................3-3
Figure 3-2. Hawk’s System Memory Controller Internal Data Paths........................3-4
Figure 3-3. Falcon Internal Data Paths (Simplified)..................................................3-4
Figure 3-3. Overall SDRAM Connections (4 Blocks using Register Buffers)..........3-5
Figure 3-4. Hawk’s System Memory Controller Block Diagram ..............................3-6
Figure 3-5. Programming Sequence for I2C Byte Write .........................................3-25
Figure 3-6. Programming Sequence for I2C Random Read....................................3-27
Figure 3-7. Programming Sequence for I2C Current Address Read .......................3-29
Figure 3-8. Programming Sequence for I2C Page Write .........................................3-31
Figure 3-9. Programming Sequence for I2C Sequential Read.................................3-34
Figure 3-10. Read/Write Check-bit Data Paths........................................................3-47
Figure 4-1. Architectural Diagram for the Universe II..............................................4-3
Figure 4-2. UCSR Access Mechanisms.....................................................................4-8
Figure 5-1. MVME2400 Series Interrupt Architecture..............................................5-2
Figure 5-2. PIB Interrupt Handler Block Diagram ....................................................5-5
Figure 5-3. Big-Endian Mode..................................................................................5-12
Figure 5-4. Little-Endian Mode ...............................................................................5-13
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